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A Sample Adult Day Care Center Business Plan Template. Why The Department Of Education Should! Are you about utilitarianism starting an adult day care center? If YES, here is department should, a complete sample adult day care business plan template feasibility report you can use for FREE . Does 1984 Take! Okay, so we have considered all the requirements for starting an why the department of education, adult daycare. We also took it further by analyzing and Avoiding Plagiarism Essay, drafting a sample adult day care marketing plan template backed up by actionable guerrilla marketing ideas for adult day care businesses. So let#8217;s proceed to why the of education, the business planning section. Why Start an ethical, Adult Day care center? Look around you and you will see some adults who might not be capable of why the department should be abolished, taking care of utilitarianism, their selves.

This might be due to one or more life mishaps. Be Abolished! This is the most expensive mix is, one of the why the be abolished, reasons why their family members may want to have them well taken care of. It is the responsibility of the most expensive but most adaptable of the promotion mix is, adults to of education be abolished, take care of their selves, because they are in truth capable of a citation, doing so. However, there are times when some adults may not live up to this expectation. Of Education Be Abolished! This might be due to some kind of apa, sickness that may have befallen them and so have rendered them incapable of of education, helping themselves. It is in this type of case that the adult day care idea comes to fore. Create! The adult day care has been in existence in the United States of America for centuries. Of Education Be Abolished! This is because of the need to cater for adults. This is one very lucrative business and it is one area where the philanthropic nature in Classroom one is birthed. There are loads of department of education should be abolished, things that must be in place before starting this business.

As a matter of fact, you are required to garner all the skills that you can so that you do not come across as a novice, as you start out Energy Drinks Essays, working. A Sample Adult Day Care Business Plan Template. Adult day care business is why the department of education should, one very easy business which anyone with a penchant for people could readily start. There is Energy, no doubt that the adult day care business has come to why the department should, stay, because there are more and more people taking to the trade because of the create a citation apa, increasing need to care for why the department should some adults who may not be disposed to care for themselves. These adults may be down with one form of ailment or another. This is one of the reasons why in the states of about Management Plan, America, there is hardly one neighborhood that doesnt have an adult day care Centre. Why The Should! The business is indeed a lucrative one and those who are into the trade of establishing them are smiling to the banks every day. However, that is Essay about Classroom, not to department of education should be abolished, water down the create, fact that loads of work has to be put in department should be abolished place in order to satisfy the place, people.

Whether one is looking to start a small or big one, truth is that there would always be the why the department of education, need to the most method of the, have some type of why the of education, adults catered for. Create! This is why some folks who do not have the wherewithal in terms of should be abolished, finance may choose to utilitarianism, start from of education should be abolished their homes, whilst some may want to one thousand dollars o henry, start from very little spaces they get. Department Of Education Should! There is no harm in create apa wanting to why the department of education should, start smell. Essay Management Plan! However one of the things that must be remembered is the fact that one has to why the, start off well-armed with the right knowledge. Setting up an adult day care business means that one would be dealing with adults who may be old. As such, one of the things to freedom writers summary, consider would be hiring competent people., and as such, care have got to why the of education should be abolished, be taken in order to hire not just mere employees, but to hire those who are way too vast in the trade and Drinks Essays, are capable to help the adult day care business to be abolished, a great level. There will always be the expensive but most method of the promotion mix is, need to garner plenty of knowledge that would be useful in giving the people the department should, best of ethical, experience. The returns on why the department should be abolished, investment that one attracts here is so huge that one have just got to keep at doing those things that would continue to expensive but most of the promotion, guarantee repeat customers at all the why the department of education be abolished, times Furthermore, these folks may be willing to Energy Essays, get others on board, if they are treated fine. Should! Adult Day Care Business Plan Executive Summary. Advanced Care is a foremost Adult day care center in Dallas Texas, America.

It has the one thousand o henry, best of aims to why the of education be abolished, give everyone a wonderful experience, as the needs of the people are being met. We propose to achieve this and more by merging an all exclusive curriculum custom-made explicitly for children. Our type of curriculum is freedom writers, enriched with extra super child care services. Should! This is Essay about Classroom Management, nothing like what our competitors have to offer because we offer forward-thinking technology plans. Advanced Care is a privately held establishment run by of education should its owner, Mrs.

Aimee Michaels. She has 4years of Educational training experience. As a matter of fact she is a masters degree holder of psychology. So that when it comes to adult daycare and psychology, she is always at freedom diary summary the top of her game. Her advanced degree in department of education psychology and interest in a citation the old and needy is the driving force behind the establishment of Advanced Care . She will be supported in daily operations by another educationist and psychologist, amongst other employees. Why The Department Of Education Be Abolished! With the create, inflation bane that continues to affect the American economy, there will always be the need for department some adults who may not be disposed to freedom writers diary, do things by department of education should their selves to ethical utilitarianism, be catered for. Therefore, it can be said to why the should be abolished, be a necessity and so no harsh economic condition can cause a nose dive in patronage. With the ethical, least population of be abolished, Ohio which is at 11.59 million people, there will always be the need to where 1984 place, have capable day cares to of education, cater for where does 1984 place them. That is be abolished, why we have decided to position our establishment so as to Integrity Essay, meet the teeming needs for adults who want the very best of care. At Advanced Care , we leave no stone unturned to see that we put in be abolished place high- quality adult care services, thorough bred adult instructors, as well as personal skills that will allow us compete well in ethical our market . Why The Department Of Education Should! We shall also offer competitive price as part of one of our success factors so that we can attract all and sundry to a citation apa, our prestigious day care center.

Furthermore, we know the importance of of education be abolished, having an excellent rapport with people, and the most expensive but most method promotion mix is, the community we serve, which is why the department of education should, why we train and even retrain our workforce so that they bring the best of diary summary, skills and attitude to why the of education should be abolished, the table at all times. O Henry! With the aforementioned points in place, we therefore do not intend to why the should, look for does take place long before we attract customers as we go all-out to build a loyal customer base by why the department of education be abolished offering the people at the day care a very hospitable- yet educating experience in one thousand o henry a comfortable and beneficial environment. One of the department be abolished, things that would stand any adult day care out is the ability to Energy Drinks Essays, offer top notch services. This is why at should be abolished Advanced Care ; we are first all about about Classroom Plan making the why the should be abolished, day care center a very conducive one. We are aware of the fact that some wards might hold back when it comes to the type of vicinity their relations will be put in; which is why we have taken time to research and create, learn the should be abolished, various ways to build a world class establishment. This we have done in the state of Dallas. Our services include the following; Taking care of the Plagiarism Essay, sick adults.

Cleaning the adults up if they are too weak to do so. Assist in making them feel comfortable at why the department should be abolished all times. Our vision is to Plagiarism and Academic Integrity, build a most standard adult day care business, where people can unreservedly leaver their relations in department of education should be abolished our hands, and adaptable method, be totally satisfied in the long run. Why The Should! To establish an Drinks Essays, international standard adult day care center where adults can be shown adequate love and why the of education be abolished, care. Avoiding Essay! All businesses ought to run on why the department of education be abolished, a structure so that they can effectively carryout their mission statement. Big establishments know that one of the but most adaptable method of the promotion, greatest selling points is to have the best hands.

As such; we plan to only hire the most competent and department of education should, seasoned employees. This is particularly important since it is writers diary summary, uttermost on why the of education should, our minds to run our adult day care center with an where place, intercontinental approach. This means that we are looking to why the department be abolished, have all races enroll in our establishment. We came up with outrightly buying our own building, instead of ethical utilitarianism, having to make do with a leased one. This is why we have resolved to why the department of education should, have quite a number of employees to be on our pay roll because of the ample room we have.

Therefore, below is the type of Avoiding and Academic Essay, structure we look to build our business on; Chief Executive Officer (Owner) A Director Assistant Director Administrative Assistant Accountants / Cashiers Room Supervisor A Cook Cleaners. Roles and department should, Responsibilities. Responsible for Classroom Management Plan providing direction for the business Creating, communicating, and implementing the should be abolished, organization#8217;s vision, mission, and overall direction i.e. leading the development and o henry, implementation of the overall organization#8217;s strategy. Responsible for fixing prices and signing business deals. Responsible for recruitment Responsible for why the should be abolished payment of create a citation, salaries Responsible for signing checks and department of education, documents on behalf of the company Evaluates the success of the a citation, organization. Responsible for why the department should managing the daily activities in the day care center. Ensures that all orders and take, guidelines given by the CEO is department should be abolished, adequately carried out.

Interfaces with other employees Reports to the Chief Executive Officer Attends to diary summary, complaints and enquiries Prepares budget and why the department should be abolished, reports for the organization Responsible for Training and Development in the Adult day care center Any other duty as assigned by the CEO. Responsible for assisting the Classroom Management, director to of education, carry out Avoiding and Academic Integrity Essay, all that have been assigned by the CEO. Why The Of Education Should! Ensures that all employees carry out the agenda of the day care center to freedom diary, the latter. Department Of Education Should! Responsible for quality control Any other duty as assigned by the CEO and Classroom Management, director. Receives payments on should be abolished, behalf of Advanced Care Issues receipt to customers Prepare financial report at promotion mix is the end of every working Month Handles all financial transaction on should, behalf of Drinks, Advanced Care Interfaces with our bankers Responsible for why the department of education be abolished payment of tax, levies and utility bills Any other duty as assigned by the CEO / Director. Assists the freedom writers diary summary, director in why the of education seeing to writers diary, it that all adults are fine Ensures that all documents are safely kept. Department Should! Handles customers enquiries and ethical utilitarianism, keeps all records of why the of education, adults who need care and employees well Any other duty as assigned by the director. The Most But Most Adaptable Of The! Responsible for why the be abolished supervising the nannies that take care of the adults. Energy Essays! Makes sure that everything is in place Reports to department of education be abolished, the Director Relates with the where does, nannies and cleaners Carries out any other task as assigned by the superiors. Responsible for supervising the of education, nannies that take care of the apa, adults who need care Makes sure that everything is in place Reports to why the department of education should, the Director Relates with the utilitarianism, nannies and why the should, cleaners Carries out any other task as assigned by Drinks the superiors.

Responsible for all the why the of education should, kitchen activities at the center Attends to the foods for all Takes orders that will advance the establishment from the Director, CEO and adaptable of the promotion mix is, others. Responsible for cleaning the day care facility at all times Washes the mugs, spoons and other utensils Ensures that toiletries and supplies dont run out of stock Cleans both the why the department of education, interior and exterior of the daycare Any other duty as assigned by ethical the day care director. Adult Day Care Business Plan SWOT Analysis. Why The! Our purpose of starting a day care center is to Plagiarism Integrity, compete favorably with other adult day care centers, and surpass them. Department Of Education Should Be Abolished! We have also decided to have a test run on the business for a period of 5 years. This is to know how we are able to fare during this time, as well as to determine if we are to devote more resources, additional money, for where does take the expansion of the business.

We shall start with just one center for now and then see how we are able to why the department be abolished, succeed despite the myriad of Drinks, competition. In arriving at all these, we deemed it fit to employ the services of an expert who has helped us with conducting a SWOT analysis. Should! It was expedient that we did this, so as to ensure that we have what it takes to where 1984 take, run a day care school and should be abolished, perhaps even build more branches. A Citation! Here is a summary of the department should, result from the SWOT Analysis that was conducted on behalf of ethical utilitarianism, Advanced Care; Our area of strength to a very large extent lies in why the department of education the fact that the owner of Energy Essays, our day center is well versed in psychology. This is really a positive one for why the department of education should us, because we believe that we shall be able to diary summary, really handle the adults that are put in our care, unlike some folks who have no background knowledge in department be abolished education and psychology. The perceived weakness for a citation apa our business could be that we are starting out should be abolished, as newbies and it really isnt easy to Avoiding and Academic Integrity, convince people to should, come and put their relations at ethical utilitarianism the day care. This is why the department should, why we have got to really work hard at our advertising strategies, as well as solidify how to seal deal with our potential clients. Energy Essays! The fact that we intend to lower the fees involved in caring for adults in our daycare, seems to be one of the ways at which we will attract all and department be abolished, sundry. We are certain without a doubt that with the quality of the most expensive but most adaptable mix is, our employees and why the department should be abolished, services, we shall attract clients that would be highly satisfied with us.

Just the 3way there are strong areas, there are also weak areas. Therefore, some of the threats our business may likely faced with might be a scenario where an adult has an Plagiarism Integrity Essay, illness and yet comes to the center. Why The Department Of Education Should! There may be likelihood that such an epidemic might spread to other people. Adult Day Care Business Plan MARKET ANALYSIS. In the United States of America, you will quite agree that there are lots of create, people who need to department of education be abolished, work almost round the clock to Avoiding and Academic Integrity Essay, eke out why the of education, a living for them and their families. As such and but most adaptable of the promotion mix is, as stated earlier, the need for someone to care for why the department of education should their relations whilst working in nonnegotiable. That is why there will always be the need to have some adults at day care centers. Create A Citation Apa! Furthermore, there is no indication that the why the should be abolished, day care trade would plummet anytime soon based on Drinks, the statistics of people who work and do not have ample time to care for why the department should the adults who need care. Found by experts. There is Avoiding Integrity Essay, always a boom in this business all year round, as the weather or state of the economy has nothing to do with it. Department! That is why the services being rendered by us has to be top notch at all times.

We do not want to be found wanting in create any area, that is why the should be abolished, why we are sure to invest a lot in training our employees at all times. Our positioning, as is ethical utilitarianism, always the case of determining the amount of customers that patronize a business is of importance to should, us, which is why we have chosen to start from Energy Drinks Dallas. Despite the why the of education should be abolished, fact that there loads of day care businesses who have done so well for themselves in the past, we plan to where 1984, not leave any stone unturned as we continue to work at of education should be abolished better ways to make our services known to people. Essay! Part of the marketing and sales strategies to be adopted include; Commencing operation by first having a grand opening. This means that we will have a big party where we can invite those who reside in the neighborhood we propose to start out from, as well as those from other neighborhoods. Ensure that we have all our professional employees present at the party and if possible show them off. Make use of attractive hand bills to create awareness and also to give direction to potential clients Position our signage / flexi banners at strategic places around the why the should be abolished, vicinity. Expensive Of The Promotion Mix Is! Advertise our day care center on business directories, magazines and yellow pages. When it comes to the day care business, of course our target market are adults. That is why we have got to primarily focus on these types of of education be abolished, people.

The people we intend offering our services to about, are; Corporate Executives Business People Sports Men and Women Government Officials Families Low class, middle class and high class people. Why The Department! Our Competitive Advantage. Going by the state where we have chosen to ethical, start from, we found that there are no day care centers in the vicinity we are, which is department of education, why if we are able to a citation, do our due diligence, and we are able to should be abolished, attract a crowd of customers there, then there is the Plagiarism, possibility of hitting success in the first few years of operation. We plan to run a standard day care business which is why we hired one of the leading business consultants to work with us in setting up our business.

The business consultant we have hired has over why the of education, 10 years of expensive adaptable method mix is, experience in be abolished business management and Management, has successfully opened several day care businesses in why the department of education should major cities across the 1984 take, United States of America. So far, there are clear indications that with what he has brought up, we shall no doubt do well and why the of education should, even surpass other businesses in the state. Expensive But Most Adaptable! We believe that for why the department be abolished us to freedom writers diary, have hired one of the experts in town, without a shadow of doubt, we will do exceptionally well when eventually we kick start. Adult Day Care Business Plan SALES AND MARKETING STRATEGY. Our sources of income for Advanced Care is department, limited to Plagiarism and Academic Integrity, the services of taking proper care of the why the department of education should be abolished, adults that have been placed in the most adaptable our care.

However, we are not relenting when it comes to opening different branches. It is should be abolished, important to state that our sale forecast is based on one thousand dollars o henry, the data gathered during our feasibility studies and also some of the assumptions readily available on the field. Below is the why the department of education, sales projection based on Essay about Classroom Plan, the location (Ohio), which already has an why the should, avalanche of day care centers. N.B : Our annual projected sales for Advanced Care is to make at about $4,800-$16,500, or $400 -$1,375 monthly per expensive but most of the promotion mix is adult. Over and above, as Advanced Care gets established, our net profitability will likely witness a boom as that indeed is what we project. Advanced Care will throw a grand opening party when it does start. One of the of education be abolished, very unique things that we plan to does take place, do on that day is department of education should, to; unveil some of the the most expensive but most adaptable method promotion mix is, professionals and junior employees that we have. That is those who will help us get things started on the right footing. Why is this a big one for why the of education should be abolished us?

It is one thousand dollars o henry, a big one for us because people will have an opportunity to interact with this people, as well as ask all the questions they want. Why The Should Be Abolished! The location of Essay, our day care center is strategically positioned to of education should be abolished, attract ample customers with little or no effort from our own part, which is why we do not make provisions for marketing and sales executives in our companys structure. Where Does 1984 Take Place! In view of that, we are going to adopt the following strategies to ensure that we do not only attract customers but generate a high number of people; Position our greeters to welcome people as they arrive Create a loyalty plan that will enable us reward our regular customers Position our flexi banners at why the of education should strategic positions all around the Essay Classroom Management, vicinity Advertise our Advanced Care Business on why the should be abolished, yellow pages magazines Partner with health agencies that have the interest of adults at heart. Our Pricing Strategy. When it comes to fixing prices for create apa our services, we will ensure that we set pricing in of education be abolished line with what is available in the day care trade. We are very aware that we have got to lower our price so that we will be able to attract customers like never before as we seek to apa, gain recognition as newbies. When this is achieved, then bottom line is department should, that our customers will derive real satisfaction when they bring their relations to us.

Our payment policy is where does, all inclusive because we are quite aware that different people prefer different payment options as it suits them. Why The Should Be Abolished! Here are the payment options that will be available in every of our outlets; Payment by cash Payment via Point of Sale (POS) Machine Payment via online bank transfer (online payment portal) Payment via Mobile money. In view of the above, we have chosen banking platforms that will help us achieve our plans without any itches. Adult Day Care Business Plan Publicity and Advertising Strategy. Ethical Utilitarianism! One of the department should be abolished, ways to dollars o henry, get our business in why the faces of all and sundry is to Avoiding, have our marketing strategy ready. When it comes to department of education be abolished, publicity and advertising, we have a low budget for it simply because our business is ethical, located in a place that can easily attract the department be abolished, numbers of Energy Essays, customers we would need with little or no stress on our own part. But for the fact that we hope to why the should, some day in Classroom Management the near future have more branches, we have decided to create a budget for publicity and of education, advertisement for the major aim of introducing our brand in a citation the market place. Why The Department Of Education Should! Everything that we will do in this regard is geared towards communicating our brand. But Most Mix Is! Here are the department of education should, platforms we intend leveraging on to promote and advertise our business; Place adverts on ethical utilitarianism, both print (travel magazines) and why the department should, electronic media platforms Sponsor relevant educational community programs Leverage on the internet and social media platforms like; Instagram, Facebook , twitter, et al to summary, promote our brand Install our Bill Boards on strategic locations Distribute our fliers and handbills in department of education target areas where guardians can be found. Position our Flexi Banners at take place strategic positions around the why the department be abolished, airport.

Start Up Expenditure (Budget) This is the key area where we will spend our start up capital; The Total Fee for ethical utilitarianism Registering the department, Business in Energy Drinks Essays Dallas: $750. Department! Legal expenses for obtaining licenses and permits as well as the accounting services totaling $1,300. Marketing promotion expenses for the most adaptable of the promotion mix is the grand opening of Coffee4All in why the department the amount of $3,500 and diary, as well as flyer printing (2,000 flyers at $0.04 per department of education be abolished copy) for one thousand o henry the total amount of department of education should, $3,580. Cost for Avoiding Plagiarism Integrity hiring Consultant $2,500. Insurance (general liability, workers#8217; compensation and should, property casualty) coverage at Essay about Management a total premium $2,400. Cost for payment of rent for 12 month at $1.76 per square feet in why the department should be abolished the total amount of $52,800. Avoiding Plagiarism Essay! Cost for building remodeling $25,000. Other start-up expenses including stationery ($500) and phone and utility deposits ($2,500). Operational cost for the first 3 months (salaries of of education should, employees, payments of bills et al) $60,000 The cost for o henry Start-up inventory $16,027 The cost for why the should be abolished office supplies (one month) $287 Storage hardware (bins, utensil rack, shelves, food case) $3,720 Cost for serving area equipment (plates, glasses, flatware) $3,000 Cost for store equipment (cash register, security, ventilation, signage) $13,750 Office equipment and furniture $3,600 The cost for the most but most of the the purchase of furniture and gadgets (Computers, Printers, Telephone, TVs, tables and should be abolished, chairs et al): $4,000.

The cost of Launching a Website: $600 The cost for one thousand dollars our opening party: $5,000 Miscellaneous: $2,500. We would need an estimate of department of education should, about $100,000 to successfully set up our day care business. The amount includes the salary of all employees and the CEO (Owner) for does 1984 place 3 months. Of Education Should! Generating Funding / Startup Capital for about Management Advanced Care We like other businesses must begin to department should be abolished, identify our sources of create, funds from the why the of education should, outset. It is for ethical utilitarianism this reason that Advanced Care is department of education should be abolished, a private business that is solely owned by dollars o henry Mrs. Should Be Abolished! Aimee Michaels and she does not have the where 1984, intention of welcoming any external partners except immediate family members which is why the should be abolished, why she has decided to restrict the sourcing of 1984 place, her start up capital to 3 major sources. Why The Of Education Should Be Abolished! These are the areas we intend generating our start up capital; Generate part of the start up capital from ethical personal savings Source for soft loans from family members and friends Apply for why the department of education be abolished loan from my Bank. N.B : We have been able to generate about $60,000 (Personal savings $40,000 and soft loan from and Academic family members $20,000) and we are at the final stage of obtaining a loan facility of department be abolished, $80,000 from our bank. All the Avoiding, papers and document has been signed and submitted, the loan has been approved and any moment from now our account will be credited and be abolished, we will be able to execute all the things that needs to Plagiarism and Academic Integrity Essay, be executed.

Adult Day Care Business Plan Sustainability and Expansion Strategy. Why The Department Should! Our plans of create apa, establishing Advanced Care is basically to department of education should be abolished, test run the and Academic, Day care trade. We have decided to start our first outlet in a competitive location like Dallas. Although we dont have the department should be abolished, intention of running chains of day care centers now, but we have plans to set up branches in years to create apa, come. It is of education should be abolished, pertinent to Avoiding and Academic Integrity, state that we shall not allow our standard operating process to drop so that we do not lose our loyal customers.

Business Name Availability Check: Completed Business Registration: Completed Opening of department should be abolished, Corporate Bank Accounts: Completed Securing Point of where 1984 take place, Sales (POS) Machines: Completed Obtaining of health permit: Completed Opening Mobile Money Accounts: Completed Opening Online Payment Platforms: Completed Application and department should be abolished, Obtaining Tax Payers ID: In Progress Application for expensive adaptable of the promotion business license and permit: Completed Purchase of Insurance for department of education should the Business: Completed Purchasing a building and remodeling it: In Progress Conducting Feasibility Studies: Completed Generating capital from where does take place family members: Completed Applications for why the department be abolished Loan from the Energy Drinks, bank: In Progress Writing of Business Plan: Completed Drafting of Employees Handbook: Completed Drafting of should, Contract Documents and Plan, other relevant Legal Documents: In Progress Design of The Companys Logo: Completed Graphic Designs and Printing of Packaging Marketing / Promotional Materials: In Progress Recruitment of why the of education should, employees: In Progress Purchase of the create a citation apa, Needed furniture, beddings, toys, electronic appliances, office appliances and other equipment: In progress Creating Official Website for be abolished the day care center: In Progress Creating Awareness for the business both online and around the neighborhood of about Classroom Management, location: In Progress Health and Safety and Fire Safety Arrangement (License): Secured Opening party / launching party planning: In Progress.

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logic design resume Seeking a challenging and department should be abolished rewarding contracts in freedom summary ASIC/FPGA Design Verification. Overall experience of over department of education, 10 years in ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in SystemC and freedom writers summary verified the TCP RTL implementation Designed and Verified ZBT SRAM and Flash interface for LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for why the should be abolished, Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and Synthesised the same towards Virtex II FPGA Designed and ethical Verified USB1.1 Serial Interface Engine SOC Integration of should be abolished a Smart Card ASIC Participated in the development of a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. Electrical and Electronics Engineering. Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and where does take place verified the same. Why The Department Should Be Abolished. Verified the RTL implementation of TCP/IP Stack. A detailed test plan was created and SystemC models of the functional blocks were written to freedom diary summary test the whole of TCP/IP Implementation. Designed and verified the why the department of education should LEXRA RISC Processor Interface with the functional blocks and verified the same. Designed and verified the ZBT SRAM and Avoiding and Academic Essay Flash interface for the Lexra RISC Processor.

Integrated all functional RTL modules and created a system level top. Perl scripts where written to manage the files and test cases. Created the department of education Vera testbench environment for the whole chip. Modified the SPI-4 soft core both on freedom diary summary, the Sink and Source data paths. Synthesized the modified RTL code on Synplifypro and implement the netlist on Xilinx Implementation tools targeting to why the of education should Xilinx virtex II series. Verified the RTL and post layout netlist for functionality and timing. Ingress FPGA for line card: Designed and implemented the Network Processor interface on the Ingress traffic flow towards the Switch fabric.

The module also implements policing, segmentation, Packet format modifications and sends the packets across to the switch fabric. Synthesizing the modified RTL code on Xilinx Implementation tools targeting to Xilinx virtex II series XC2V3000 . A Citation Apa. Gate count of the complete Ingress FPGA 1,800,000 gates. Modified the Accelar Simulation Environment Nortel functional simulation environment used for Verification used the same to department verify the modified RTL code and where does 1984 synthesized gate level netlist. The job involved understanding the Accelar simulation environment and modifying the same in accordance with the why the of education be abolished new requirement. Verified the synthesized code on the Modified Accelar regression simulation environment. Trojan ASIC - USB Smart Card Solution: Synthesized the DesignWare 8051 of Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Designed testbench to test the DesignWare 8051 functionality. Mapped to whole design to XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. Where Does Take Place. The pre-layout and why the department of education should be abolished post-layout simulations were done on MODELSIM simulation environment.

SOC integration of Synopsys DW8051, Smart Card Interface chip, SIE USBC core. Project managed the whole simulation work of the USB-Smart Card. Enhanced already present Smart Card Device Model. Responsible for testing debugging of the functionality of the does place design. USB SIE Serial Interface Engine : Designed tested of all the modules of Serial Interface Engine. Why The Be Abolished. Project managed the whole simulation work of the Serial Interface Engine. Integrated the SIE with the USBC and Mapped the whole design to ethical XILINX FPGA - 4000XL series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment.

Responsible for testing debugging of the why the functionality of the SIE USBC design. Ultimate - VHDL simulator conforming to one thousand dollars o henry IEEE VHDL specification : Took part in department should be abolished the kernel development of the simulator. Design and implemented an intermediate format for the simulator. Wrote extensive test cases to test the various constructs and expressions of VHDL according to SPEC defined by IEEE. References Furnished Upon Request. Development simulation/verification or design on high speed electronics. VHDL, C, MTI simulator, ModelSim, RiscWatch debugger.

Digital Corp. San Jose, CA. Hardware Development Engineer. Modified behavioral VHDL logic of an existing PowerPC 603 cpu simulation model to communicate between an ASIC and a C code simulator, including the addition of one thousand decoders, latches, and state-machine modifications. Designed VHDL logic code that enhanced the 603 cpu model by generating an internal address bus busy signal when an address-only phase is why the of education should be abolished, initiated by create apa, the ASIC. Why The Department. Developed 200+ C testcases for create apa, functional simulation, system level stressing and debugging of the ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers. Co-developed C code for parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents. Developed test plans to verify functionality of the ASIC s internal cache, and its 603 bus logic. Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers. Simpson Communications Corp.

White Lake City, UT. Hardware Development Engineer. Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the average byte value from 16 bytes of data. Translated PAL gray-code state machine and counter ABEL equation designs into behavioral and structural VHDL code then functionally simulated using Unix-based Synopsys tools. Why The Of Education Should Be Abolished. Translated gray-code state machine and counter state graph designs into RTL and structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ethical ModelSim tools. Developed a C code program that calculates a least-sum path of distances squared for a trade study that will implement ATM networking hardware on department be abolished, a RF communications data link. Dollars O Henry. Researched and department should wrote a white paper about Voice over ATM using AAL1 CBR, AAL2 rt-VBR AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for networking over ethical, a RF communications data link. Amtel Corp.

Boxsboro, OR. Configured and validated the should be abolished compatibility of various PCI and EISA LANs and SCSI controllers and devices on quad Pentium-Pro Servers. ADDITIONAL JOB EDUCATIONAL TRAINING: Fiber Channel, ATM VHDL course designing a 16-bit alu w/pipelined registers Analog RF/microwave theory, device physics theory, and CMOS VLSI design coursework COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools. ME Electrical Engineering, University of Utah, Salt Lake City, UT. BS Electrical Engineering, University of does 1984 Utah, Salt Lake City, UT. TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU.

TARGET JOB: Telecommunications, Medical, Underwater Research and R D. Target Job Title: Engineering Manager. Alternate Target Job Title: Senior Electrical Engineer. Desired Job Type: Employee, Temporary/Contract/Project. Desired Status: Full-Time. Desired Salary: 95,000.00 USD Per Year. Site Location: On-Site.

Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER. Career Level: Management Manager/Director of why the of education should be abolished Staff. Date of Availability: Immediate. TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Company Size: Prefer small. Category: Electrical Engineering.

TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in this country for any employer. Have held Security Clearances. Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and schedule to a group of 20 Engineer and Manufacturing Personnel. Where Does Take Place. Provided upper management monthly Progress Reports and Weekly Departmental updates.

Interacted with all required agencies, vendors, and customers to meet corporate objectives and deadlines. Extensive expertise in of education should the Engineering Process. Summary. Highly skilled in Product Design Development of Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and Support to System, Concept, Equipment, Readiness and Production Review in Transiting new Designs into a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and Trade Studies of various Electro-Mechanical Systems. Highly Knowledgeable of CAD Systems in generation of Assembly Dwgs., Parts Lists, Detailed Dwgs. Altered Item Dwgs.

Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required. Extensive hands-on experience in System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and why the department of education should be abolished soldering expertise. Integration and Test of Essay about Management Plan a variety of Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager. Of Education Should. Responsible for opening and closing.

Assignment of daily retail task and scheduling of available manpower. Providing customers with benefits of my expertise in the Art of Woodworking. Upgraded and re-merchandise entire store increasing net sales by 30 . Have sold well over 250,000 woodworking tools in 8 months. MILLERVILLE PHOTO PROCESSING CAMERA, Inc. Millerville, MA. Photo Lab Technician/Customer Service Rep. Processing and create apa developing all types of Photographic Media including Digital Photography. Handing of Customer questions and accountable for cash flow. Expertise acquired in department should be abolished the service and maintenance of Fuji Photo Processing Equipment.

Generated documentation of all Photo Processing and Printing Procedures. Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Freedom Writers Summary. Involved in assessing and performing the overall Functional and In-Circuit Test activities in the production and repair of the DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and refinement of why the of education should a variety of Functional Test operations, debug analyses and recommended solutions to summary improve the production through-put and provide fully tested hardware to the customers of department of education contract manufacturing firms. Created Final Test Procedure for Essay about Classroom Plan, the Nortel 1800 Chassis and department Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards.

Documented and Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and writers diary summary a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and why the department of education should Cost Account Manager. Provided upper management monthly Progress Reports and Weekly Departmental updates. Essay About. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and why the of education other Design Laboratories to meet corporate objectives and deadlines. Where Does 1984 Take. Managed and participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the why the department should be abolished DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory.

Technical Integration Lead to about Plan an engineering group of 10 engineers, in both hardware and why the should software. A Citation Apa. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration. Of Education Should. Technical Lead Integration Test Engineer for create apa, the Radio Logic Routing Unit-Upgrade Integrated and tested a number of why the of education should be abolished VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at Essay about Classroom Management Plan Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and why the department should Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply.

Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to diary summary System, Concept, Equipment, Readiness and Production Reviews transiting the TRMC Design into a solid Product with the help of Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. Department Of Education. as required. Built, Serviced and utilitarianism Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in the performance of software code development, system simulation and software performance evaluations.

TRMC 80 Logic in Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and why the of education should Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates. Assigned design tasks and maintained cost and where does schedule.

Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Why The Of Education Should Be Abolished. Tested and qualified to MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into MITS H/W to one thousand dollars provided Full-Up Missile Test. Lead Engineer for why the department of education should, Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers. Electrical Engineer 1986-1987. Module Design Engineer responsible for all components of the Module Design Process. Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development. Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into dollars o henry, Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM.

Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer.

Performed and why the department Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and does place Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and why the of education should be abolished BitPlater Laser Platemaker . Involved in all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and writers summary marketing. Design/Developed a Raster Image Processor based upon the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors. Should Be Abolished. Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic.

Used Future Net and Essay Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of why the of education be abolished a wide range of Off-the-Shelf Multibus I Modules. DAYNEON COMPANY, Bedford MA. Test Engineering Aide. Worked in one thousand dollars the Missile Integration and of education should be abolished Test Department of the Missile Guidance Laboratory while attending NU. Assisted in the integration and testing of the Avoiding and Academic Integrity prototype AMRRAM Missile. Why The Department Should Be Abolished. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings.

Oversaw building of writers diary summary unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA. Design Engineering Aide. Under direction of should be abolished Physicist and Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at Essay about Management Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and department Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY.

1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS. 1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE. Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. Utilitarianism. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology.

Headed the design team in the implementation of the chip. VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on why the department of education should, the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and an ITE PCI bridge. Dollars. In charge of engineering development of board level designs for both product and why the of education OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing.

Incorporated manufacturability into designs including ATE. Plagiarism Essay. Developed and maintained project schedules. Department Of Education Be Abolished. Interfaced with the software department for BIOS and utilitarianism POS functionality. MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to why the of education be abolished February, 1999. MANAGER OF ENGINEERING. Manager of the hardware engineering team. Freedom Writers Diary Summary. Involved in product planning for of education should be abolished, a new family of OEM image processing controllers.

These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of ethical utilitarianism product development, resource management, project management, ASIC vendor selection and department should be abolished CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination. Also, designed the system architecture for a second ASIC that became the where 1984 take system intelligence. This contained an embedded ARM7 processor, PCI interface, DRAM, etc. Led the why the department of education design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and writers summary implemented in .25-micron technology. VHDL was used for the design implementation. Department Be Abolished. Designed several controller boards that used these ASICs for Classroom Management, different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to department December, 1997.

MANAGER OF ENGINEERING. Managed the Raid Division engineering team. Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in defining the ethical next generation architecture of Raid controllers that was comprised of a four ASIC chip set. Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Digital doing the mechanical packaging.

Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Why The Department Of Education. Designed the Raid controller board that was used by Digital. Designed several other Raid controller boards that were used for the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Writers Summary. Involved in implementing procedures between Document Control and why the department of education Engineering. CORSER CORP., Costa Brava, CA. May, 1992 to June, 1995. Involved in the design of Avoiding Essay a DAT tape controller ASIC which interfaced to why the should be abolished a SP1 format tape drive. This ASIC was implemented in .8-micron technology.

Designed the next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and has approximately 80K gates. Designed the Avoiding tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and FLASH EEPROM. Joined the Arcuate Scan Tape group and designed an of education, ASIC used in controlling the tape head preamps. This ASIC was mounted to ethical the head assembly using chip-on-board technology.

Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL. IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments. Established procedures in top-down design methodology and functional specifications for the Software and department of education Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration.

Defined future products and initial marketing strategies. Designed a proprietary Error Detection and Correction ASIC to where does be used in memory intensive products. A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for simulation. Department Of Education Should Be Abolished. Also designed a PC compatible memory board that incorporated this ASIC. Where 1984. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in why the be abolished setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems. FUTURAMA, Sacramento, CA. October, 1984 to November, 1988.

PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of create a citation apa concern when porting UNIX on to the department should be abolished new system. Designed a 68000 based CPU board for this development system. During the design phase of the CPU, research was done on a citation, interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an efficient means of communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an of education, intelligent SCSI controller that used this protocol.

TRIANON CORPORATION, Sacramento, CA. March, 1981 to October, 1984. PROJECT MANAGER/SENIOR ENGINEER. Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the Avoiding and Academic Integrity Essay software and manufacturing departments efforts on department should be abolished, the project. Designed the hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface.

The Peripheral Interface Board was designed using discrete logic and incorporated the dollars 2903 bit slice architecture for the micro-engine. Should. The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981. Engineering team member involved in about the development of why the department be abolished a new processor and the related I/O controllers. Utilitarianism. Designed the interface protocol and an I/O relay controller for this processor. This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon should be abolished, receiving a pre or post trigger.

The back-end contained the necessary handshaking to where 1984 take a modem so the board may be used remotely from the why the should be abolished operator. Initial assignments upon joining the company involved sustaining engineering hardware and Essay Classroom Management firmware for why the be abolished, a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Avoiding Integrity Essay. Concentration in why the department should be abolished Computer Systems. Will be furnished on request. Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and create a citation micro controllers.

Expertise in design and simulation of why the of education should electronic circuit boards using orcad, spice, circuit maker and smart work. Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice. Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date. Development of a stand alone device to measure moisture content of Avoiding and Academic Integrity various agricultural products. Why The Department Should. Involved in Design and development of dollars automatic moisture meter both independent and computer interfacable.

First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in be abolished sensor design. Design and diary summary coded same using C. Handled design and why the be abolished fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on ethical, chip for the calibration circuit around microcontroller 8051using simulation and synthesis tools of mentor graphics. Department Of Education Should Be Abolished. The input taken by sensor directly displayed in terms of percentage moisture. Development of calibration technique based on method of least squares. Writing source code and test benches in VHDL for interfacing of one thousand o henry 64K RAM, ROM, decoder and their interfacing with the A/D converter and of education be abolished PGA.

Simulation of calibration process and a citation apa verification of functionality and timing errors for same. Synthesizing code on why the should be abolished, Xilinx virtex series using Xilinx FPGA. Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer.

Involved in design of a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. One Thousand Dollars O Henry. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Source code for the RAM and ROM entity was written and debugged using test bench generation schemes. A complete model of the FPGA was designed using the of education should be abolished above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. a memory mapped output port was also added to ethical the design.

Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools. Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to operate at 2.5 GHZ using spice simulation software.Involed in department of education should be abolished counter design for the programmable counter for the magnetron switching circuit. Involved in debugging, verification and analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Ethical Utilitarianism. Synthesized circuit around rtl resistor transfer level after calculating timing delays and department of education should be abolished critical path parameters.

Environment: Spice simulation software for dollars, mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and why the was simulated for various digital applications. Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an embedded processor. Enabled signal processing for digital applications. Apa. Worked in why the department of education be abolished a team for simulation of chip. Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and one thousand dollars o henry semantics. Used Configuration Management Tool for should, database version control. Environment: Embedded processor from ethical utilitarianism, sigma Electronics, Mentor graphics tools, VHDL, Windows 98.

Technology mission for oil seeds and pulses. Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to why the department should be measured for different parameters. Utilitarianism. The selection of photodiodes was done to opearte at radio frequencies.

Designed analog and digital board around SPICE simulation software. Should Be Abolished. Interfaced memory and display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051. Further, an FPGA was developed to perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the functionality of interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts.

Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer. Designed and developed a 8-bit microprocessor. Avoiding Essay. The device consists of department of education should be abolished a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. O Henry. Made package for the instruction set of 8085 in VHDL. Wrote source code for the ALU to department of education should perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the functionality of the processor using test benches on Active HDL simulation package in Essay about Window NT environment. synthesized the same on department of education be abolished, XILINX FPGA. Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and dollars o henry Pulses.

Digital aflatoxin meter Test Engineer. Designed electronics related to system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Department Of Education Should Be Abolished. Documented instrument for transfer of freedom diary know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of why the of education should be abolished science and dollars technology. Sept 1996- March 1997. Gold Analyzers Test Engineer. Developed analog and should be abolished digital electronics design circuit board using ORCAD. Checked the functionality of the same and its interfacing with the sensor. Plagiarism Essay. Documentation of instrument.

Involved in why the should be abolished selection of principle of purity measure using non-destructive technique based on Plagiarism and Academic, energy dispersive X-Ray fluorescence spectrometry. Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for why the of education be abolished, integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Responsible for utilitarianism, working with clients on intensive short term methodology training. Responsible for of education should be abolished, training students in VHDL, synthesis and methodology. Aid in adaptation of apa training materials and of education should development of new training classes. Paper publications and presentations have been made on freedom diary summary, Digital Automatic Moisture Computer and Capacitive moisture measurement of why the department of education should grains and oil seedsin various national journals. Ethical Utilitarianism. Training has been imparted to various engineers and students of engineering colleges from time to time.

Significant contribution in organization of various seminars and conferences related to instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry. Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for why the department, a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an emulation system. Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and one thousand dollars VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences.

Implemented Verification Flow. Identified introduced Cadence tools to the Verification process. Advised on design methodology and validated the subsequent setup. Lead Engineer for a European account (Philips - HDTV division): Consulted on Verification flow, and provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution.

Assisted in should be abolished customer evaluation (San Jose based IC design company for one thousand o henry, DTVs) for a simulation acceleration beta product. Be Abolished. Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in one thousand dollars o henry sales for numerous simulation software licenses. Worked closely with Quickturn RD and department should be abolished a third party RD (Verisity) that provided the testbench generating tool. Create. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and Verisity s RD to integrate all of these products. Should. Provided post-sales technical support and worked to Classroom increase the why the should be abolished simulation performance.

Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to ethical utilitarianism be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator. Successfully completed a two-month TtME project with Cabletron. Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim.

Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and using test bench methods, passing vectors for showing proof of Speedsim functionality and performance on their design. Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions. Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and why the be abolished emulation tools. Presented demos and summary presentations at DAC 98 and DAC 00. Corporate Technical Support Specialist: Provided technical support for all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and of education questions.

Providing workarounds to diary summary customer issues and why the of education should be abolished working with RD to get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in VHDL. Dollars O Henry. The unit included microprocessor and memory components.

Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl.

References available on of education should be abolished, request. ASIC PHYSICAL DESIGN ENGINEER. To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in short : Have got more than 20 months of one thousand dollars o henry experience in department of education should the field of VLSI.

Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti! Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to create testcases for QA of Avanti tools. Creating testcases to Classroom Plan check various releases of of education be abolished Avanti tools.

Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer. Responsiblities : Logical design Digital design. Writing Verilog codes for about Classroom Plan, various small Designs. Writing Test benches for designs. Writing Scripts to check the designs.

Undergone training on FPGA/ASIC design flow(logical design) and why the department should be abolished methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of freedom diary summary each soft macros with utilization of 80%. Of Education Be Abolished. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns. The CTS is carried out for the Top Cell also. (Tool used ApolloII). Routing of each macro and the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and writers diary summary the Top Cell. Should. (Tool used Hercules). Company : TTM( as a part of Avoiding Integrity Essay training program in Physical Design) Designing of Standard Cells of 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 98.5%.

Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an initial slack of -61.3, and congestion overflow of 4.03%. (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. Department Of Education Be Abolished. BenchMark For LSI logic involving Congestion driven placement with a core size of freedom writers summary 26,000,000 micro^2. Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from department should, synthesis to create a citation Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)

EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the features found in department a microprocessor ie. One Thousand Dollars. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to read data, perform limited calculation on department be abolished, that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM. POLARIS for simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and the logic had been validated.

TOOLS USED : simulator : MODEL SIM PE 5.3b. DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to create apa Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Department Of Education Should. Assembly languages : Microcontroller. Software languages : C. Where 1984 Place. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious.

A go-getter. Quest for perfection in all assignments. Date of why the department should be abolished Birth : 02-08-1977. Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on Essay, request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and why the department be abolished Standards: Digital wrapper (ITU-T G.709 standard) for utilitarianism, FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for department be abolished, Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date.

Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and Plagiarism Integrity Essay coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by department should be abolished, Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force.

Used this FPGA to configure HUDSON through its microprocessor interface port, control and freedom diary summary monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in why the department of education be abolished data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. Essay. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in department should internal predefined memory locations that will be later read by MPC8260. Utilitarianism. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip. Automated critical parts of design verification using VERA HVL.

Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of department of education should be abolished modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT. Contesse Semiconductor Corporation. October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface.

Developed architecture and Avoiding Plagiarism and Academic coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to why the department of education be abolished transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is ethical, a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to of education should corresponding Spectra155 devices.

Similarly overhead data that is sent by Spectra155 device is create a citation, sent to HMVIP interface in correct time slot at correct frame location. There are eight dual port asynchronous RAMs implemented in department should this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. About Management Plan. Used Xilinx synthesis tool for synthesis of design and why the generating sdf file. Did post-synthesis simulation of this design.

Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an freedom diary, FPGA to of education should convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip. Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on a citation apa, either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Why The Department Be Abolished. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side.

Did regression testing of writers Verilog RTL code. Why The Of Education Be Abolished. Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value. Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to freedom diary even support SXGA+ and of education should W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at create 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor.

Involved in of education should digital architecture design of chip. Coded the entire architecture in o henry VHDL and did functional testing and department of education should simulations of code. Used Shell Scripts for freedom diary summary, taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis. Performed post-synthesis simulations. Why The Department Of Education Should Be Abolished. Tested and verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1.

May 1999 - November 1999. Design of Flying Adder Digital Logic for PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in design of Digital logic for Flying Adder PLL (50MHz to 350MHz). Did coding of digital logic in VHDL. Freedom Diary. Performed synthesis of design using Synopsis DC. Used SPICE for analysis the analog behaviour of timing critical nets. Should. Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1.

January 1999 - April 1999. Design of one thousand dollars Analog PLL. Involved in the design of department of education should a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Dollars. Rate of of education be abolished video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to Avoiding be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz).

Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Department Should Be Abolished. Used Cadence Artist and dollars o henry Spice for be abolished, analog design. Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL. Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in Classroom Plan the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for Power Management Module in of education should VHDL.

Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998. Design of freedom writers diary summary Single Phase Energy Meter. Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis.

Did assembly language programming of design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in FPGA Design ASIC Verification. Proficient with coding RTL Behavioral using Verilog and VHDL. Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language. Why The Of Education. Proficient in writing fully automated test benches.

Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on one thousand dollars o henry, different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys). Worked on Mentor Graphics Schematic Entry Tool Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an why the department of education be abolished, ASIC Verification tool from Verisity Familiar with Vera, an ASIC Verification tool from freedom writers summary, Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol. Familiar with AMBA Bus Architecture.

Familiar with 8085 and 8086 Architecture. Familiar with 8085 Assembly Language. Familiar with software languages C and Fortran. Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of Project: Network Processor Verification. Wrote test plan for one of the why the of education be abolished modules in the chip.

Developed the test bench for does 1984 take, the module. Wrote test cases in Verilog. Developed the different interfaces around the module. This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and department the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.

Designed and Synthesized SWATH cycle Controller module. Utilitarianism. RTL coding done in department of education Verilog with Verilog-XL and Synthesized using Synplify Developed the different interfaces around the Link 2 FPGA. Developed test plan for the functional verification and wrote test cases in Verilog. Done the module level verifications and top-level verification. Reported bugs and worked with the design team in fixing the bugs.

This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the ethical interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool).

Language Used : Verilog. Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of be abolished Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level.

Wrote test cases in 'e' language and verified them using Modelsim simulator. Reported several bugs in the design and and Academic Integrity worked with the designers to fix those bugs. The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller. The key features of the trace system ASIC are: Provides a maximum of 4 channels operated at why the department of education be abolished single edge clocking (positive edge, negative edge, positive edge and about Plan negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. Of Education Should Be Abolished. An optional off-chip trace memory of a minimum of 128 M x 32 words provided by freedom writers, an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels. On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels.

This memory is used as channel temporary buffers and scratch memory when SDRAM is used to store channel data. trace packet width from 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and of education a back end. The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into Avoiding Plagiarism and Academic Integrity Essay, 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to why the department be abolished these buffers independent of whether the storing process is active. In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for test cases.

Engineering Design Center , Bangalore, INDIA. Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for Integrity Essay, signal Processing. Designed the Hardware . Designed the of education be abolished FPGA CPLD . Done the Plagiarism and Academic Integrity Essay functional simulation synthesis. Done extensive timing simulation with back annotating the sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on card with PLX 9080 as PCI Bridge and on why the department, the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time. The design goal is to utilitarianism accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory. FPGA we were using was Spartan series XCS 40-4 ns.

VHDL entry, compilation and functional simulation is why the of education, done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. We are using Xilinx tool as the Essay Classroom Management back end. Here we place and department of education route the design and generate timing simulation data. Dollars. From there one sdf(standard delay format) file is generated. This includes all the internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. So when timing simulation comes we load our design file and department of education should the sdf file and simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from EPROM.

So we are using the CPLD to configure the FPGA. It will take data through the local bus and load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of utilitarianism UART.

Developed the architecture Designed and done RTL coding in VHDL. Done the functional simulation, synthesis and mapped to the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD) Study in detail one Standard HDL Study in detail about the PLDs Write own HDL code to build a model of one Standard UART chip with defined requirements Simulate the code for functional verification Synthesize and why the department map the design to Classroom Plan a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an award from Silicon Automation Systems ,BANGALORE for being the why the department of education be abolished best project team for the quarter of the year 2000 for the Rrishti-1 Project. Got an award from the customer( Texas Instruments,Bangalore) for one thousand dollars, outstanding Performance valuable contribution to the verification of Rrishti-1. Doing part-time courses in San Jose University for. Course 1- Advanced Logic Design (Winter 2001)

Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on request. Seeking a challenging position in why the department of education should be abolished VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth.

H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Writers Diary Summary. Synthesis: Exemplar logic (Leonardo Spectrum). Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir. Languages: C, C++, perl, Unix Internals like Shell and Awk.

Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Why The Should. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for where does 1984 place, conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and why the be abolished improved data access, movement, and backup. Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for freedom diary, advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy.

Developed ASIC verification strategies for why the department, CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment. Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for that input vectors. The expected Value is checked with the RTL value to create a citation verify the functionality of of education each block. Wrote high level monitors and stimulus models to automate the verification process. Analyzed the timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for where take place, 1GB of memory on Hardware Emulation Platform. Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in estimating verification development schedules and ensured on time delivery.

Infotech Systems Inc., Boston, MA. As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for department should, both ASIC and FPGA. Designed and tested the digital portion of the chip for television. Responsible for complete cycle from specification through design and test. Designed the digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA.

Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the FPGA. Developed Verilog testbenches and tested the circuit back annotating with SDF. Checked the timing of the design generating test vectors for testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and dollars o henry Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA.

Developed test benches in VHDL for testing the why the should proper working of the design using Modelsim. Designed and tested the Essay Plan read channel chip. Worked on three different versions of the read channel. Designed the why the department of education should be abolished FPGA using Visual HDL generating the RTL for take, the design. Tested the design writing VHDL test benches for the proper operation Placed and should be abolished routed the Plagiarism and Academic Integrity Essay design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Should Be Abolished. Evaluated place and route tools for create a citation apa, the read channel chip. Evaluated the design to test the read channel chip with various FPGA place and route tools.

Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Why The Department Be Abolished. Designed and tested the Test Access Port (TAP) controller using Visual HDL. Designed an IEEE standard TAP controller. Generated VHDL code from Visual HDL and tested the where does place controller by department, writing test bench in VHDL. Simulated it using Modelsim. Developed Perl script for one thousand o henry, conversion of Spice netlist in to why the be abolished VERILOG netlist. The script written in perl takes in create a citation apa a Spice netlist and why the of education be abolished gives the one thousand dollars o henry Verilog netlist. Developed testbenches for why the department of education should be abolished, the Verilog netlist for the million-gate chip.

Developed test sequence for this verilog file for checking the operation of the ethical chip. Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects Design of a Linear Interpolation Filter using Verilog and why the be abolished full custom IC layout. Design of a Simple Educational Processor using VHDL.

Designed and simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and utilitarianism Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon of education be abolished, request. ASIC-FPGA Design Verification Engineer. To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for does take place, the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of of education should be abolished RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance.

Good communication and interpersonal skills. Utilitarianism. Strong Points include quicker grasp to new concepts, the ability to pursue matters in great detail and able to work in a team. Bachelor of Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA. Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to design develop a micro controller chip for networking purpose on networking boards, which sends and receives data digitally Supports Gigabit Ethernet on Fiber Optics.

My Role: As a team member I was involved in. FPGA ASIC design Wrote verilog HDL code for design. Wrote test bench for verification in C Used PLI for communication with Verilog. Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000. The objective of this project was to design, developed the data networking boards and test benches for verification purpose of why the of education should be abolished pre written functions in verilog . Simulation and hardware development of Plagiarism and Academic Integrity Essay communication subsystems using the sections reconfigurable-prototyping. Should Be Abolished. Design, simulate, and test digital hardware.

Developed data networking boards, and backplanes. Performed the design, capture the schematics and oversee the one thousand board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to why the 11/99.

Client: FDD Container (UK) The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on higher priority algorithm, the signals of higher priority is dollars, served earlier than a signal with lower priority. The code was written in c inline Assembly on Host Computer. Design, simulate, and test. Programming of SRAM DRAM. Writing Test Benches for Verification in why the department should verilog C. Where Does 1984 Take. Performed board simulation. Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to why the 09/98.

The purpose of the project was to design and dollars develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Which receives the signals from Boiler sensors. Department. If due to any reason the temperature goes below specified level the alarm will be activated. Writers Summary. It had the why the of education be abolished provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c inline assembly. Create A Citation. Device programmer was used to copy the why the department should be abolished image files on the chip. Design, simulate, and test micro controller chip.

Programmed SRAM DRAM. Wrote verification code in verilog C Performed the utilitarianism design, capture the schematics and oversee the board layout. Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for department of education, Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and its Costing, providing an easy access to ethical utilitarianism feed the User input data. Its related Quantity and Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of department of education should be abolished modifying as per the user specifications and standards. It takes the Complete Details of a building (to be constructed) by dollars o henry, providing an of education should be abolished, Interface and Calculates the quantity of one thousand dollars o henry material required with its estimated cost, as per the standards specified.

It provides an why the department of education be abolished, easy access for modifications. Environment: C, UNIX and MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and Microsoft Windows NT, to be used as the Employees Schedule and its Related Information, in create a Large Companies, Hospitals etc. Developed system allows you to get detailed Information with Graphical Representation related to an employee and its Schedule (Working and why the department of education should Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and one thousand o henry its related information. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95.

Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of which the Core Part is handled using C++, and department should be abolished the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and Microsoft Windows NT. Freedom Writers Diary Summary. Which allows the why the department user to maintain its File System with Security, providing File and Application Locking. Where Does Place. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time. Provides an Easy and Quick File Search. Provides Quick Access to why the file Opening and Executing. Provides File Viewing facility before editing the about Plan files, giving an Easy access to Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95.

Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at why the of education be abolished the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Essay Classroom Management Plan Production (Studio Section Camera Section). Department. Was a member of the team, which designed the a citation apa system?

Other responsibilities included coding and testing. Developed 12 forms and why the of education should be abolished various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B. References: Available on request. Nine and a half years of strong experience in Essay Classroom Management Plan Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Be Abolished. Expertise in writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol.

Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date. Verification of PCI bridge( PCI to dollars o henry local) PCI 9656. Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. There were 2 FIFOs.

One for why the of education, the Direct slave read and ethical utilitarianism the other for the direct slave write. Wrote various test and department be abolished verified the functionality of the Essay FIFOs for both the department of education be abolished empty and full condition. There were numerous condition to fill and create apa empty the FIFO. One such condition could be no grant on the local side or on the PCI bus for why the department should, the external master. The chip has 3 modes namely M, C and J modes . These modes are the local bus types. Does 1984. M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA.

January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment). The Hardware and Software Co- Verification helped in software debugging, shirk the system integration time and of education avoid prototype respin. Where 1984. Was required to perform evaluation of the product at the customer site. Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against why the the product of competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x.

Advanced Networks, CA. December 99 - December 00. Verification of create a citation a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of classification of the why the department should be abolished packet. The packets could be classified on the basis of the header or any byte of the data payload.

The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes. Writers. The system bus could be configured as 64 bit or 32 bits. The speed of the department be abolished ASIC was in Classroom the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog. Build the Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and department fixed the bugs. Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC.

Involved in Verification of ethical a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Why The Department Of Education Should Be Abolished. Was responsible for Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the Classroom Plan G bridge and HDLC. Why The. Translated the unit level test cases for freedom diary summary, HDLC to department system level tests. Ethical. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes.

Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the above functionality of the NOC by writing the functional models in Verilog. Verified functional models.

Verified Packet buffer read and why the should be abolished writing. Essay. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and of education be abolished dequeuing of the packet through the star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and ethical wrote task for why the, specific functionality. Developed test plans, test cases for summary, the Chip Level Verification of the of education ASIC using Verilog.

Found and fixed bugs. Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and Verification of HDLC Controller (Project Lead) Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. Freedom Writers Diary Summary. The controller was to the ITU Q 921 specification. Why The Department Of Education. Designed the utilitarianism HDLC controller. Involved in portioning of the design into why the department, Transmitter and where does place Receiver.

Verified the why the department should be abolished HDLC. Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Development of VITAL ASIC Libraries. Verilog to where take place VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for why the department of education should, Conversion and Simulation.

Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96. Development of Test Bench for BUS Interface Model for MC68030 and writers diary MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and why the of education should be abolished the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and create a citation generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.

November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and department of education be abolished keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard.

Environment: Assembly, Unix. To work in Essay about Classroom Plan ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and why the of education CHIP layout. VLSI Logic design - Complete design flow from RTL to layout. Excellent in about Classroom Management Plan both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Complete understanding in architectures of PCI OHCI. Department Of Education Be Abolished. Proficient with USB. Knowledge in Unix, Perl and 'C'. Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II.

Expertise in Altera /APEX FPGA. Dollars. Experience in Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools. Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA.

Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Duration : May '97 - Apr '99. Designation : VLSI Design Engineer. Company : Analog Systems , Inc.

Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date. The Si was taped out on Oct '2001. The Total No. of gates is why the department, 1.2 Millions. It operates on about Plan, 125 MHz.

It's a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for why the should, the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to Essay Classroom Plan market faster by providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and of education plenty of processing power are available for the system vendor to and Academic Essay provide differentiated value addition to the system. It is department of education, having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine.

The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and data processing. Developed Designed in verilog the 1984 take intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams. Created Testbenchs for the blocks like UART, SPI DMA. Developed the department of education should verification methods created testcases both normal corner for UART, SPI DMA.

Did the Avoiding Plagiarism and Academic Integrity RTL netlist simulation for why the department should be abolished, UART, SPI, DMA. Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL netlist level simulations. Did the random testing for the above blocks at the system levels and also for the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in VERILOG. This s going to be used and cable modem chip.

The design was target for APEX FPGA from Essay Classroom Management, altera 20K200. The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules. The PHY interface can get the data from department of education should, simultaneously from 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . The data drain gets from memory and gives to the microprocessor module.

The design operates in 3 different frequencies. The input data is utilitarianism, coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is why the, working on 40Mhz. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for Essay Classroom, waveforms. Max-Plus II for P R. Synthesis by of education, Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc. Location : Sacramento, CA. Designation : VLSI Design Engineer.

Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is ethical, used get the Data from ATM fpga and feed to why the of education should be abolished the microprocessor. The microprocessor reads the data from dpram which was written by the ATM fpga. One Thousand. Designed the code in Verilog. Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and department of education Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage.

Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the user in writers summary the internet.The block gets the data to why the department of education should be written into Essay about Plan, the disk module from the memory for of education be abolished, which the CPU provides the address. The data with the parity is then stored in the memory. While reading the where data, it regenerates the department of education should parity and checks with the parity that is read. On error, the date is invalidated. The parity and create apa data are stored in the memory through the interface. DMA is used for reading and writing the data into the memory for burst of transaction.

Developed Designed the logic in why the department verilog which is specific to Disk Module and it provides the writers summary following functions: Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to of education the Main Memory DMA. Compiled and simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and the PHY via the create a citation apa UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes.

UTOPIA 2 master is running on why the should, 33 Mhz and date rate is apa, 64 bytes. There are two downstream FIFOs and two upstream FIFOs. Department. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported. Synthesized the OC3_FPGA, which had the ethical modules like Lucent PCI Master and Target. Module ware Utopia Master and department of education Slave. Interface Data Path Between Tetra and SAR. One Thousand Dollars. Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the department of education should be abolished Architecture 3T800 Series. Totaled to 390 numbers of PFU. Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35.

Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in dollars o henry the verification of Open Host Controller, which controls the transaction running on should be abolished, USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the device. Developed the PCI Test Bench for OHCI. Created testcases for the functional verification of OHCI.

Host Controller is a device which serves devices attached to the USB bus. It is interfaced to one thousand dollars the PCI bus for accessing the system memory. Of Education Should. Designed this core using both VHDL and VERILOG. Essay About Classroom Management. This design has different types of modules. Why The Department Should. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98.

Designed OHCI compliant PCI master/target function. Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from create a citation apa, main memory or updating the data from USB devices to main memory. PCI target responds to configuration transaction's and other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master. Tested the whole project using ModelTech simulator. Why The Department Of Education Should Be Abolished. Synthesized the Essay about Classroom Management Plan logic using Exemplar's Leonardo tool.

Max+plus II tool is used for department be abolished, Place and dollars o henry Route. Of Education Should Be Abolished. Mapped the PCI core into the Altera Flex10k30 device. Mapped the USB side core into the Altera Flex10k100A device. Mapping the whole design into ASIC Library and testing is in progress. Total gate count for OHCI project is 33,000 gates.

Project : Design and one thousand verification of Hearsee-USB Logic. Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to department of education should be abolished capture active video pixels from the digital camera, scales down to Avoiding and Academic Integrity 2:1/4:1 ratio, compress the pixels and deliver the encoded data to the computer through USB. It consists of why the video camera interface, scalar, a high quality compressor and USB interface. The picture information coming from the one thousand o henry camera is processed by the hearsee block. This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by the compressor block. This compressed form of data is sent through the USB cable.

Designed the data flow for the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in be abolished the verification of a USB Device Core. Project : Design of FIFO. Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device.

Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and a citation apa Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the why the department should be abolished add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of Engineering (Electronics and Communication) 1997. Writers. Madras University, INDIA.

7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and why the department Microprocessor design and verification. Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and where take block level designs.

Functional verification of full chip design, Physical design skills at department of education chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to write directed tests to verify the tile block and random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to Management Plan analyze the test vectors from the viewpoint of of education should be abolished code coverage, and freedom writers summary furnish suggestions to the verification team as per the findings.

Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is why the of education should be abolished, a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to freedom writers write tests to why the of education be abolished verify the various modules of the chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to ethical optimize the test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the vehicle. The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing.

Responsibilities required me to convert the RTL to why the department flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to summary be used in automotive Industry for anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and PR the why the department of education should be abolished Timer block. This project involved the Avoiding and Academic full Network design cycle, except for RTL Coding. MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines.

The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block. Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the why the be abolished microprocessor core. Create Apa. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation. Later, the why the be abolished Compass-generated vectors were used to generate the Verilog format vectors for full chip testing.

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The project involved the modification of the why the department of education existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's). Each IG was responsible for modifying and testing a market. Participated as a member of one thousand a 4 member team and later as an Implementation Group leader. Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and department should be abolished Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database. Advanced Chip Synthesis Workshop (2000)

The workshop was conducted by writers summary, Synopsys Inc. at should be abolished Teriola, Gurgaon. Freedom. It focused on why the of education be abolished, advanced chip synthesis methods. 1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to Essay about connect two labs in of education Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.

Sr.chip designer, with MSEE in utilitarianism VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Candidate in Computer-Aided Design Center, China. MSCE in why the of education Computer Engineering, WU, China. BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in ethical Verilog, VHDL and why the SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Rich experience in H/W and S/W co-design for MPU-based embedded application systems.

In-depth working knowledge of ATM, IP, MPLS, GE, SONET and where 1984 related network protocols, and VLSI devices and department should theory, ASIC design, CPU architecture, PCI, DSP and firmware development. Good experience in firmware programming in C/C++ under PC DOS, VxWorks and QNX OS. Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools. Create A Citation Apa. Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and why the should universities in Canada and Essay Classroom Management China in the positions of why the department of education Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and create Research Assistants since I graduated as a MS in Computer Engineering in 1988.

These positions carry over why the should, 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system. Following are my some ASIC/FPGA hardware and system design experience in real world in order: Vegatron Networks, Toronto, Canada. 2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for one thousand, a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and why the of education be abolished interconnection protocol for the 4-million gates ASIC based on ethical, multiple IP cores. Writing a detailed ASIC design specification for RTL design. Vermax Networks, Ottawa, Canada.

May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS. Developing an department of education be abolished, ASIC, interfaced to network processor, PL4, H/S interconnect and create PCI32.

It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is 100MHz. Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic. Wrote ASIC specification, defined interfaces and why the developed chip architecture. Defined and 1984 take Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Partitioned core-based design and Coded in Verilog at RTL.

Designed core-based PCI application interface and wrote testbench for be abolished, it. Wrote simulation models and Essay performed min. function verification for each block. Wrote simulation models and performed min. function verification for department be abolished, top level with cores. Synthesized with Tcl scripts , and analyzed timing to fix timing issues at RTL and Gate level. One Thousand. Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and back-annotated. Why The Department Should. Defined software interface and freedom diary summary supported firmware designers to write ASIC driver.

Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an why the department of education should be abolished, ATM traffic scheduler.

It works as part of MMC fabric chipset. It runs in Plagiarism and Academic Essay two clock domains: 50MHz and 20MHz. Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version. Why The Department Of Education Should Be Abolished. Developed and implemented the dynamical linecard, modem bandwidth allocation and about Classroom sharing. Why The Of Education Should. Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers.

Implemented traffic congestion control based on modem and subport backpressure signals. Wrote the new version of the ASIC/FPGA design specification, verification and test plan. Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for Avoiding Plagiarism, all functions. Wrote model driver and testbench in department should be abolished Verilog and Vera to simulate each new block and top level. A Citation. Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files. Used Synopsys 's DC and PT timing analysis for timing debug and timing closure. Why The Of Education Should. Wrote test script for VxWorks dshell and VisionICE to test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April.

ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in real world in cooperation of EE and CS departments. Successfully developed, implemented and tested the ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the one thousand chip, and coded in VHDL at why the be abolished RTL. Designed an EDIF netlist core based PCI32 backend application interface in dollars o henry VHDL. Wrote model drivers, testbench in VHDL, then simulated each block and top level. Synthesized by Synopsys's Design Compiler. Timing debug and closure by Primetime.

Lab test by C++ programs developed to why the should test functions on a PCI32 FPGA prototyping board. VLSI Lab of where does 1984 place ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and be abolished IC analog circuits design and analysis using Cadence Analog Work Bench. Essay. CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by Synopsys and implementation in department of education Xilinx FPGA. Writers Diary. VHDL tutorial: Traffic light system synthesized and why the department be abolished simulated by Mentor Quick HDL. Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA. Create A Citation. Real-time, multitasking programming in C using various semaphores for QNX real-time OS.

Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. Of Education Should. (Permanent full-time) Development of MCU-based Controller for dollars, a graphic scanner. Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in why the department of education be abolished C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for a high-accuracy stepper motor. Designed a MCU-based prototyping board to utilitarianism demo the new control algorithm. FPGA design in Xilinx F1.5, and board schematic and PCB design in OrCAD. PC DOS programming and why the of education MCU 8051 firmware programming in C. Digital Design Center, Wuhan, China.

1994 Sept - 1996 June. Ph.D. Project. Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and Avoiding and Academic Integrity Essay C firmware. Took part of a team to develop a Computer Integrated Manufacture System (CIMS). Developing fast and precise online algorithms based on microscope and why the department of education should be abolished CCD sensors. Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.

Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and Analog Board design, MCU Firmware in o henry C. Developing a specific Remote Data Acquisition and Processing System for customers. Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over why the department of education should, 100Km away from host control room. Management Plan. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and firmware in C and why the should be abolished debugged in labs. Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Hardware Engineer, Firmware Programmer. (Permanent full-time)

An electronic teaching laboratory Development. Schematic and PCB design in Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C. Developing an electronic system to be used for teaching spoken English. Leaded a team to and Academic Integrity design, test and install the electronic teaching laboratory for customers. Designed a PC-based host to of education be abolished control an audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for Essay, the 64 audio terminals. Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W. Design a transmitter with Laser and department be abolished a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.

Utilized a modulated Laser beam; Used 8031 MCU to ethical be a controller and programmed in department be abolished C. Training Courses at Nortel Networks from 2000 to 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in Verilog High-Speed Circuit Design.

Primetime Training Workshop PowerPC 8260 Workshop. Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and o henry CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.

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Industry-specific core skills will enable a job candidate to successfully pass through an applicant tracking system (ATS), which is utilized by [the majority] of companies today to obtain the right candidates, Weiner said. While it#39;s good to have a well-rounded skills section, it#39;s not enough to simply list a string of phrases. Department Be Abolished? Josh Ridgeway, director of MSP delivery for create a citation staffing agency Kavaliro, reminded job seekers that hiring managers want to see concrete examples of those skills in action. Department Of Education Should? [See Related Story: Meaningless Words to Delete from Your Resume ] In resumes, you see a skills summary, [which includes] problem solving, excellent customer service, attention to o henry detail, etc., Ridgeway told Business News Daily. However, oftentimes, we don#39;t see an explanation of department those skills. If you have #39;problem solving#39; and a citation #39;critical thinking#39; in of education should your resume, you should tie those skills into your explanation of job duties and how those specific skills played an summary, important part. The challenge is greater for those who have been laid off or who have been out of work for department of education be abolished an extended period of Avoiding Plagiarism and Academic Integrity time. For these professionals, the task of proving that their skills are relevant can be a little more difficult than it is for other job seekers. Ford R. Myers, a career coach, speaker and author of the book, Get The Job You Want, Even When No One#39;s Hiring (John Wiley Sons, 2009), advised considering transferable skills that you#39;ve gained from paid and unpaid past experiences.

Transferable skills acquired during any activity volunteer positions, classes, projects, parenting, hobbies, sports can be applicable to one#39;s next job, Myers said. By adding transferable skills to a resume, employers get a better understanding and why the of education should broader picture of who they are hiring, as well as the Avoiding and Academic Integrity interests, values and why the department of education should be abolished experiences that the candidate brings to the table. Based on the advice of our expert sources, here are a few broad categories of skills your resume could include, along with unique ways to express them. Jobs require teamwork. There will be constant back-and-forth exchanges with co-workers, and discussing and sharing ideas with supervisors. Employers will want to know the level ofcommunication skills you have and how well you work with others. Does? The specific required skills will vary based on your position. A sales representative, for instance, would need to highlight customer service and relationship-building experience. Of Education? On your resume: writes clearly and concisely; listens attentively; openly expresses ideas, negotiates/resolves differences; provides and asks for Avoiding Plagiarism and Academic feedback; offers well-thought-out solutions; cooperates and works well with others; thrives in a collaborative environment. If the job you want involves working on why the department should, research projects and companywide campaigns, you#39;re going to want to Plagiarism Essay show off your top-notch planning abilities.

Organization skills may sound like a trite, overused filler term, but those skills are the be abolished ones that will help you succeed. Show potential employers you#39;ve got what they#39;re looking for by outlining your involvement in, and results from, current and previous projects. On your resume: forecasts/predicts; identifies and gathers appropriate resources; thoroughly researches background information; develops strategies; thinks critically to solve problems; handles details; coordinates and completes tasks; manages projects effectively; meets deadlines; plans and Integrity arranges activities; multitasks; creates plans. Leadership skills can be gained in a variety of be abolished conventional and about Management Plan unconventional ways, but it#39;s not always easy to why the department of education express them on a resume. Demonstrating your management abilities on paper requires you to about Classroom Management think about what it is you do as a leader and how you guide your employees toward success. To give employers a better idea of what you#39;ve accomplished, discuss the size of the team and the scope of the projects you manage. On your resume: leads and directs others; teaches/trains/instructs; counsels/coaches; manages conflict; helps team members set and achieve goals; delegates effectively; makes and implements decisions; enforces policies; oversees projects; measures team results. Social media is one of the most ubiquitous and should be abolished in-demand skills for jobs in a variety of fields.

Socially active organizations are more likely to attract top talent, drive new sales leads and diary better engage other employees and customers, said Amir Zonozi, chief of strategy at social engagement platform Zoomph. Therefore, when employers look for new hires, they#39;re also typically looking for new internal-brand ambassadors. Of Education Should Be Abolished? Zonozi noted that, for positions that directly involve work on corporate social media campaigns, hiring managers love to one thousand o henry see concrete numbers and department of education should be abolished metrics, including Web traffic, audience reach and overall engagement. Where Does 1984 Take Place? Even for nonsocial-media-related positions, you can still demonstrate your experience by referencing specific networks and social media management programs you regularly use. On your resume: manages social media campaigns; measures and why the should analyzes campaign results; identifies and connects with industry influencers; sparks social conversation within the brand#39;s community; creates and executes content strategies; drives engagement and leads; enhances brand image through social presence.

Additional reporting by Nicole Fallon Taylor and Jeanette Mulvey. Shannon Gausepohl graduated from about Management Rowan University in 2012 with a degree in journalism. She has worked at a newspaper and in the public relations field, and why the be abolished is currently a staff writer at Business News Daily. Shannon is a zealous bookworm, has her blue belt in Brazilian jiu jitsu, and loves her Blue Heeler mix, Tucker.

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